1. Field of the Invention
The present invention relates to a high voltage switch circuit and a semiconductor memory device provided with the same and, more particularly to a structure performing voltage control and ensuring a normal switching operation.
2. Description of the Background Art
Conventionally, a high voltage switch circuit has been used as a circuit for converting the amplitude level of an input signal. The high voltage switch circuit converts an input signal (amplitude level VCCxe2x88x92GND) switching between a power supply voltage level VCC and a ground voltage level GND to a signal (amplitude level VPPxe2x88x92GND) switching between a positive high voltage level VPP and a ground voltage level GND or to a signal (amplitude level VNxe2x88x92VCC) switching between a negative high voltage level VN and power supply voltage level VCC (|VN| greater than VCC).
The high voltage switch circuit includes a transistor (a switching transistor) for switching and a transistor for voltage control. A high voltage is applied between the source and drain of the switching transistor during the switching operation, during which hot carriers are generated to cause degradation of the current value or threshold value of the transistor. Thus, a normal operation of the circuit cannot be ensured. Accordingly, the transistor for voltage control is arranged to control the voltage of the transistor.
Such a high voltage switch circuit is used for controlling data writing, reading, erasing and the like, with respect to a memory cell of the semiconductor memory device.
However, in the conventional high voltage switch circuit, a gate voltage of the transistor for voltage control is fixed at a prescribed value (at power supply voltage VCC when switching at high voltage VPP and at ground voltage GND when switching at high voltage VN).
Thus, the conventional structure suffers from a problem that the circuit cannot operate if the switching high voltage is close to power supply voltage VCC or ground voltage GND. In addition, in the semiconductor memory device, a memory operation must be controlled by using a high voltage switch circuit ensuring a normal switching operation and optimum voltage control.
Therefore, the present invention provides a high voltage switch circuit ensuring a normal switching operation and optimum voltage control as well as a semiconductor memory device provided with the same.
A high voltage switch circuit according to one aspect of the present invention includes: a first power supply node capable of supplying a high voltage greater in absolute value than a power supply voltage; a second power supply node to supply a voltage at most the power supply voltage; a first transistor converting the voltage level of an input signal in accordance with the input signal and the voltage supplied from the first power supply node; a second transistor converting the voltage level of an input signal in accordance with the input signal and the voltage supplied from the second power supply node; a switch circuit switching the amplitude level of an input signal between the power supply voltage level and the ground voltage level; and a third transistor connected between the first and second transistors and having its gate voltage controlled.
Preferably, the third transistor operates such that the drain-source voltage of the first or second transistors is controlled.
More preferably, the gate voltage of the third transistor is switched by a control signal for making the first power supply node attain to a high voltage.
Preferably, the voltage of the first power supply node attains to a high voltage when a first period of time is elapsed after it is at a power supply voltage. The gate voltage of the third transistor is switched by a signal activated when a second period of time shorter than the first period of time is elapsed after the voltage of the first power supply node begins to change.
Preferably, the gate voltage of the third transistor is switched by a signal activated when the voltage of the first power supply node attains to a prescribed level.
Preferably, the gate voltage of the third transistor is controlled by a control signal at a voltage level which is less dependent on the power supply voltage. It is noted that the above mentioned voltage may arbitrarily be changed.
Preferably, the gate of the third transistor is controlled by a bias voltage allowing a constant current which does not depend on the high voltage.
Thus, according to the above described high voltage switch circuit, the gate voltage of the transistor for voltage control can be controlled. Accordingly, the voltage of the transistor is controlled when the voltage of the power supply node attains to a desired high voltage level. In addition, a normal operation is ensured even if the power supply node is at the low voltage level.
Particularly, the gate voltage of the transistor for voltage control can be controlled by a control signal for making the voltage level of the power supply node attain to the high voltage level.
Particularly, the gate voltage of the transistor for voltage control can be controlled by a signal activated when the voltage level of the power supply node increases or decreases.
Particularly, the gate voltage of the transistor for voltage control can be controlled by a signal activated when the voltage of the power supply node attains to a desired level.
Particularly, the gate voltage of the transistor for voltage control can be controlled by a signal which is not dependent or less dependent on the power supply voltage.
Thus, optimum voltage control is achieved without stopping the operation of the circuit.
A semiconductor memory device according to another aspect of the present invention includes: a memory cell array including a plurality of memory cells; a control circuit for controlling the operation of the memory cell array; a circuit generating an operation signal for operating the memory cell array under control of the control circuit; a generation circuit outputting a power supply voltage in a stand-by mode and activated during the operation of the memory cell array for generating a high voltage greater in absolute value than the power supply voltage; and a high voltage switch circuit switching the amplitude level of the operation signal. The high voltage switch circuit includes: a first power supply node receiving a voltage output from the generation circuit; a second power supply node supplied with a voltage at most the power supply voltage; a first transistor converting the voltage level of the operation signal in accordance with the operation signal and the voltage supplied from the first power supply node; a second transistor converting the voltage level of the operation signal in accordance with the operation signal and the voltage supplied from the second power supply node; a switch circuit switching the amplitude level of the operation signal; and a third transistor connected between the first and second transistors and having its gate voltage controlled.
Preferably, the third transistor operates such that a drain-source voltage of the first or second transistors is controlled.
More preferably, the control circuit includes a circuit generating a control signal for activating the generation circuit, and the gate voltage of the third transistor is switched by the control signal.
More preferably, the control circuit includes a circuit generating a control signal for activating the generation circuit and a delay circuit for delaying the control signal by a prescribed period of time for output. The gate voltage of the third transistor is switched by an output from the delay circuit.
More preferably, the control circuit includes a circuit generating a control signal for activating the generation circuit and a circuit generating a detection signal which is activated when an output from the generation circuit attains to a prescribed level. The gate voltage of the third transistor is switched by the detection signal.
More preferably, the operation signal switches between the power supply voltage and the ground voltage. The control circuit includes a signal generation circuit generating a control signal at a voltage level which is less dependent on the power supply voltage. The gate voltage of the third transistor is switched by the control signal. It is noted that the above defined voltage may arbitrarily be changed by the signal generation circuit.
More preferably, the operation signal switches between the power supply voltage and the ground voltage. The control circuit includes a circuit generating a bias voltage to be supplied to the gate of the third transistor such that a constant current, which is not dependent on the high voltage, flows to the third transistor.
Thus, according to the above described semiconductor memory device, the gate voltage of the transistor for voltage control can be controlled in the high voltage switch circuit switching the voltage level of the operation signal for the memory operation. Accordingly, voltage control is achieved in accordance with the memory operation, thereby enabling a normal operation if the memory operation is performed or not.
Particularly, the gate voltage of the transistor for voltage control can be controlled by a control signal activating the circuit generating the high voltage.
Particularly, the gate voltage of the transistor for voltage control can be controlled by a signal obtained by delaying the control signal activating the circuit generating the high voltage.
Particularly, the gate voltage of the transistor for voltage control can be controlled by a signal activated when the voltage output from the circuit generating the high voltage during the operation of the memory cell array attains to a prescribed level.
Particularly, the gate voltage of the transistor for voltage control can be controlled by a signal at a voltage level which is not dependent or less dependent on the power supply voltage.
Therefore, according to the semiconductor memory device of the present invention, a normal operation and voltage control of the high voltage switch circuit are ensured, so that an accurate operation is ensured.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.